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1 lt1336 half-bridge n-channel power mosfet driver with boost regulator n floating top driver switches up to 60v n internal boost regulator for dc operation n drives gate of top n-channel mosfet above supply n 180ns transition times driving 10,000pf n adaptive nonoverlapping gate drives prevent shoot-through n top drive maintained at high duty cycles n ttl/cmos input levels n undervoltage lockout with hysteresis n operates at supply voltages from 10v to 15v n separate top and bottom drive pins the lt ? 1336 is a cost effective half-bridge n-channel power mosfet driver. the floating driver can drive the topside n-channel power mosfets operating off a high voltage (hv) rail of up to 60v (absolute maximum). in pwm operation an on-chip switching regulator maintains charge in the bootstrap capacitor even when approaching and operating at 100% duty cycle. the internal logic prevents the inputs from turning on the power mosfets in a half-bridge at the same time. its unique adaptive protection against shoot-through cur- rents eliminates all matching requirements for the two mosfets. this greatly eases the design of high efficiency motor control and switching regulator systems. during low supply or start-up conditions, the undervoltage lockout actively pulls the driver outputs low to prevent the power mosfets from being partially turned on. the 0.5v hysteresis allows reliable operation even with slowly vary- ing supplies. features descriptio n u n pwm of high current inductive loads n half-bridge and full-bridge motor control n synchronous step-down switching regulators n 3-phase brushless motor drive n high current transducer drivers n class d power amplifiers applicatio n s u , ltc and lt are registered trademarks of linear technology corporation. typical applicatio n u + + + sv + pv + uvout intop inbottom 16 14 13 12 11 9 8 1 2 10 5 3 4 switch boost tgatedr tgatefb tsource bgatedr bgatefb lt1336 i sense 1n4148 200 m h* hv = 40v max** c boost 1 m f 10 m f 25v 12v pwm 0hz to 100khz 1336 ta01 irfz44 irfz44 6157 1000 m f 100v sgnd pgnd swgnd 1n4148 r sense 2 w 1/4w * sumida rcr-664d-221kc ** for hv > 40v see ?eriving the floating supply with the flyback topology?in applications information section intop inbottom tgatedr bgatedr l l l l l h l h h l h l h h l l
2 lt1336 absolute m axi m u m ratings w ww u supply voltage (pins 2, 10) .................................... 20v boost voltage ......................................................... 75v peak output currents (< 10 m s) .............................. 1.5a input pin voltages .......................... C 0.3v to v + + 0.3v top source voltage ..................................... C 5v to 60v boost-to-source voltage (v boost C v tsource ) ............................ C 0.3v to 20v switch voltage (pin 16) ............................ C 0.3v to 60v operating temperature range commercial ............................................ 0 c to 70 c industrial ........................................... C 40 c to 85 c junction temperature (note 1)............................ 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c package/order i n for m atio n w u u order part number lt1336cn lt1336cs lt1336in LT1336IS 1 2 3 4 5 6 7 8 top view n package 16-lead pdip 16 15 14 13 12 11 10 9 i sense sv + intop inbottom uvout sgnd pgnd bgatefb switch swgnd boost tgatedr tgatefb tsource pv + bgatedr s package 16-lead plastic so narrow electrical characteristics symbol parameter conditions min typ max units i s dc supply current (note 2) v + = 15v, v intop = 0.8v, v inbottom = 2v 12 15 20 ma v + = 15v, v intop = 2v, v inbottom = 0.8v 12 14 20 ma v + = 15v, v intop = 0.8v, v inbottom = 0.8v 12 15 20 ma v + = 15v, v tsource = 40v, v intop = v inbottom =3040ma 0.8v (note 3) i boost boost current (note 2) v + = 15v, v tsource = 60v, v boost = 75v, 3 5 7 ma v intop = v inbottom = 0.8v v il input logic low l 1.4 0.8 v v ih input logic high l 2 1.7 v i in input current v intop = v inbottom = 4v l 725 m a v + uvh v + undervoltage start-up threshold 8.4 8.9 9.4 v v + uvl v + undervoltage shutdown threshold 7.8 8.3 8.8 v v buvh v boost undervoltage start-up threshold v tsource = 60v, v boost C v tsource 8.8 9.3 9.8 v v buvl v boost undervoltage shutdown threshold v tsource = 60v, v boost C v tsource 8.2 8.7 9.2 v i uvout undervoltage output leakage v + = 15v l 0.1 5 m a v uvout undervoltage output saturation v + = 7.5v, i uvout = 2.5ma l 0.2 0.4 v v oh top gate on voltage v intop = 2v, v inbottom = 0.8v, l 11 11.3 12 v v tgate dr C v tsource bottom gate on voltage v intop = 0.8v, v inbottom = 2v, v bgate dr l 11 11.3 12 v v ol top gate off voltage v intop = 0.8v, v inbottom = 2v, l 0.4 0.7 v v tgate dr C v tsource bottom gate off voltage v intop = 2v, v inbottom = 0.8v, v bgate dr l 0.4 0.7 v t jmax = 125 c, q ja = 70 c/ w (n) t jmax = 125 c, q ja = 110 c/ w (s) consult factory for military grade parts. test circuit, t a = 25 c, v + = v boost = 12v, v tsource = 0v and pins 1, 16 open. gate feedback pins connected to gate drive pins unless otherwise specified.
3 lt1336 v is i sense peak current threshold v tsource = 60v, v boost = 68v, v + C v isense 310 480 650 mv v ishys i sense hysteresis v tsource = 60v, v boost = 68v 25 55 85 mv v sat switch saturation voltage v isense = v + , v boost C v tsource = 9v, l 0.85 1.2 v i sw = 100ma v bout v boost regulated output v tsource = 40v, v intop = v inbottom = 0.8v, 10 10.6 11.2 v i boost = 10ma, v boost C v tsource t r top gate rise time v intop (+) transition, v inbottom = 0.8v, l 130 200 ns measured at v tgate dr C v tsource (note 4) bottom gate rise time v inbottom (+) transition, v intop = 0.8v, l 90 200 ns measured at v bgate dr (note 4) t f top gate fall time v intop (C) transition, v inbottom = 0.8v, l 60 140 ns measured at v tgate dr C v tsource (note 4) bottom gate fall time v inbottom (C) transition, v intop = 0.8v, l 60 140 ns measured at v bgate dr (note 4) t d1 top gate turn-on delay v intop (+) transition, v inbottom = 0.8v, l 250 500 ns measured at v tgate dr C v tsource (note 4) bottom gate turn-on delay v inbottom (+) transition, v intop = 0.8v, l 200 400 ns measured at v bgate dr (note 4) t d2 top gate turn-off delay v intop (C) transition, v inbottom = 0.8v, l 300 600 ns measured at v tgate dr C v tsource (note 4) bottom gate turn-off delay v inbottom (C) transition, v intop = 0.8v, l 200 400 ns measured at v bgate dr (note 4) t d3 top gate lockout delay v inbottom (+) transition, v intop = 2v, l 300 600 ns measured at v tgate dr C v tsource (note 4) bottom gate lockout delay v intop (+) transition, v inbottom = 2v, l 250 500 ns measured at v bgate dr (note 4) t d4 top gate release delay v inbottom (C) transition, v intop = 2v, l 250 500 ns measured at v tgate dr C v tsource (note 4) bottom gate release delay v intop (C) transition, v inbottom = 2v, l 200 400 ns measured at v bgate dr (note 4) symbol parameter conditions min typ max units electrical characteristics test circuit, t a = 25 c, v + = v boost = 12v, v tsource = 0v, and pins 1, 16 open. gate feedback pins connected to gate drive pins unless otherwise specified. the l denotes specifications which apply over the full operating temperature range. note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: lt1336cn/lt1336in: t j = t a + (p d )(70 c/w) lt1336cs/LT1336IS: t j = t a + (p d )(110 c/w) note 2: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see typical performance characteristics and applications information sections. note 3: pins 1 and 16 connected to each end of the inductor. booster is free running. note 4: see timing diagram. gate rise times are measured from 2v to 10v and fall times are measured from 10v to 2v. delay times are measured from the input transition to when the gate voltage has risen to 2v or decreased to 10v.
4 lt1336 typical perfor m a n ce characteristics u w dc supply current vs supply voltage supply voltage (v) 4 supply current (ma) 16 22 20 18 16 14 12 10 8 6 1336 g01 8 6 101214 20 18 both inputs high or low v tsource = 0v v intop = high v inbottom = low v intop = low v inbottom = high dc + dynamic supply current vs input frequency input frequency (khz) 1 supply current (ma) 60 50 40 30 20 10 0 10 100 1000 1336 g03 v + = 20v 50% duty cycle c gate = 3000pf v + = 15v v + = 10v dc supply current vs top source voltage top source voltage (v) 0 supply current (ma) 30 34 31 28 25 22 19 16 13 10 1336 g18 10 5 152025 40 35 both inputs high or low v + = 12v v intop = high v inbottom = low v intop = low v inbottom = high dc supply current vs temperature temperature ( c) ?0 supply current (ma) 100 18 17 16 15 14 13 12 11 10 9 1336 g02 0 25 25 50 75 125 both inputs high or low v intop = high v inbottom = low v + = 12v v tsource = 0v v intop = low v inbottom = high input frequency (khz) 1 supply current (ma) 60 50 40 30 20 10 0 10 100 1000 1336 g04 c gate = 10000pf c gate = 1000pf 50% duty cycle v + = 12v c gate = 3000pf dc + dynamic supply current vs input frequency temperature ( c) ?0 supply voltage (v) 100 13 12 11 10 9 8 7 6 5 4 1336 g05 0 25 25 50 75 125 shutdown threshold start-up threshold undervoltage lockout (v + ) temperature ( c) ?0 input current ( m a) 14 13 12 11 10 9 8 7 6 5 4 0 50 75 1336 g08 ?5 25 100 125 v + = 12v v in = 4v top or bottom input pin current vs temperature input threshold voltage vs temperature temperature ( c) ?0 input threshold voltage (v) 100 2.0 1.8 1.6 1.4 1.2 1.0 0.8 1336 g07 0 25 25 50 75 125 v low v high v + = 12v temperature ( c) ?0 v boost ?v tsource voltage (v) 100 13 12 11 10 9 8 7 6 5 4 1336 g06 0 25 25 50 75 125 shutdown threshold start-up threshold v tsource = 60v undervoltage lockout (v boost )
5 lt1336 typical perfor m a n ce characteristics u w temperature ( c) ?0 turn-on delay time (ns) 100 400 350 300 250 200 150 100 1336 g14 0 25 25 50 75 125 bottom driver top driver v + = 12v c load = 3000pf turn-on delay time vs temperature top gate rise time vs temperature temperature ( c) ?0 bottom gate rise time (ns) 100 230 210 190 170 150 130 110 90 70 50 1336 g10 0 25 25 50 75 125 c load = 10000pf c load = 3000pf c load = 1000pf v + = 12v temperature ( c) ?0 bottom gate fall time (ns) 100 210 190 170 150 130 110 90 70 50 30 1336 g11 0 25 25 50 75 125 c load = 10000pf c load = 3000pf v + = 12v c load = 1000pf bottom gate fall time vs temperature input voltage (v) 4 input current (ma) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 8 9 1336 g09 567 10 11 12 v + = 12v top or bottom input pin current vs input voltage bottom gate rise time vs temperature top gate fall time vs temperature temperature ( c) ?0 top gate fall time (ns) 100 1336 g13 050 180 160 140 120 100 80 60 40 20 25 25 75 125 c load = 10000pf c load = 3000pf v + = 12v c load = 1000pf temperature ( c) ?0 top gate rise time (ns) 100 300 280 260 240 220 200 180 160 140 120 100 80 1336 g12 0 25 25 50 75 125 c load = 10000pf c load = 3000pf v + = 12v c load = 1000pf temperature ( c) ?0 turn-off delay time (ns) 100 400 350 300 250 200 150 100 1336 g15 0 25 25 50 75 125 bottom driver top driver v + = 12v c load = 3000pf turn-off delay time vs temperature temperature ( c) ?0 lockout delay time (ns) 100 400 350 300 250 200 150 100 1336 g16 0 25 25 50 75 125 bottom driver top driver v + = 12v c load = 3000pf lockout delay time vs temperature temperature ( c) ?0 release delay time (ns) 100 400 350 300 250 200 150 100 1336 g17 0 25 25 50 75 125 bottom driver top driver v + = 12v c load = 3000pf release delay time vs temperature
6 lt1336 typical perfor m a n ce characteristics u w pi n fu n ctio n s uuu i sense (pin 1): boost regulator i sense comparator input. an r sense placed between pin 1 and v + sets the maximum peak current. pin 1 can be left open if the boost regulator is not used. sv + (pin 2): main signal supply. must be closely decoupled to the signal ground pin 6. intop (pin 3): top driver input. pin 3 is disabled when pin 4 is high. a 3k input resistor followed by a 5v internal clamp prevents saturation of the input transistors. inbottom (pin 4): bottom driver input. pin 4 is disabled when pin 3 is high. a 3k input resistor followed by a 5v internal clamp prevents saturation of the input transistors. uvout (pin 5): undervoltage output. open collector npn output which turns on when v + drops below the undervolt- age threshold. sgnd (pin 6): small-signal ground. must be routed separately from other grounds to the system ground. pgnd (pin 7): bottom driver power ground. connects to source of bottom n-channel mosfet. bgatefb (pin 8): bottom gate feedback. must connect directly to the bottom power mosfet gate. the top mosfet turn-on is inhibited until pin 8 has discharged to below 2.5v. bgatedr (pin 9): bottom gate drive. the high current drive point for the bottom mosfet. when a gate resistor is used it is inserted between pin 9 and the gate of the mosfet. pv + (pin 10): bottom driver supply. must be connected to the same supply as pin 2. t source (pin 11): top driver return. connects to the top mosfet source and the low side of the bootstrap capacitor. tgatefb (pin 12): top gate feedback. must connect directly to the top power mosfet gate. the bottom mosfet turn-on is inhibited until v tgate fb C v tsource has discharged to below 2.9v. tgatedr (pin 13): top gate drive. the high current drive point for the top mosfet. when a gate resistor is used it is inserted between pin 13 and the gate of the mosfet. boost (pin 14): top driver supply. connects to the high side of the bootstrap capacitor. swgnd (pin 15): boost regulator ground. must be routed separately from the other grounds to the system ground. pin 15 can be left open if the boost regulator is not used. switch (pin 16): boost regulator switch. connect this pin to the inductor/diode of the boost regulator network. pin 16 can be left open if the boost regulator is not used. v boost regulated output vs temperature i sense voltage threshold vs temperature temperature ( c) ?0 i sense voltage threshold (mv) 100 1336 g20 050 0.52 0.50 0.48 0.46 0.44 0.42 0.40 0.38 0.36 25 25 75 125 high voltage threshold low voltage threshold v + = 12v v boost = 68v v tsource = 60v temperature ( c) ?0 v boost regulated output (v) 100 1336 g19 050 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 25 25 75 125 v boost ?v tsource v + = 12v v tsource = 40v i load = 10ma
7 lt1336 fu n ctio n al diagra uu w + + sv + sv + i sense intop inbottom boost trip = 10.6v trip = 8.7v 16 switch swgnd tgatedr tgatefb tsource pv + bgatedr 1336 fd sgnd pgnd bias 3k 2 4 5 6 1 3k top uv detect bottom uv lock 2.9v 2.5v 480mv 5v 5v 6v uvout + 15 14 13 12 11 10 9 bgatefb 8 3 7
8 lt1336 test circuit switch swgnd boost tgatedr tgatefb tsource pv + bgatedr i sense sv + intop inbottom uvout sgnd pgnd bgatefb 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 3k 50 w 50 w 1 m f 1 m f 3000pf 1336 tc01 lt1336 200 m h* 1n4148 * sumida rcr-664d-221kc 2 w 3000pf + v/ i + v/ i + v + v + v + v/ i + v ti i g diagra u w w 10v 2v intop inbottom top gate driver bottom gate driver 2v 0.8v 2v 0.8v 12v 0v 12v 0v t r t d1 t d3 10v 2v t r t d2 t d4 t f t d3 t d2 t f t d4 1336 td t d1
9 lt1336 floating supply. this allows the output to smoothly transi- tion to 100% duty cycle. an undervoltage detection circuit disables both channels when v + is below the undervoltage trip point. a separate undervoltage detect block disables the high side channel when v boost C v tsource is below 9v. the top and bottom gate drivers in the lt1336 each utilize two gate connections: 1) a gate drive pin, which provides the turn-on and turn-off currents through an optional series gate resistor, and 2) a gate feedback pin which connects directly to the gate to monitor the gate-to-source voltage. whenever there is an input transition to command the outputs to change states, the lt1336 follows a logical sequence to turn off one mosfet and turn on the other. first, turn-off is initiated, then v gs is monitored until it has decreased below the turn-off threshold, and finally the other gate is turned on. the lt1336 incorporates two independent driver chan- nels with separate inputs and outputs. the inputs are ttl/cmos compatible; they can withstand input voltages as high as v + . the 1.4v input threshold is regulated and has 300mv of hysteresis. both channels are noninverting drivers. the internal logic prevents both outputs from simultaneously turning on under any input conditions. when both inputs are high both outputs are actively held low. an internal switching regulator permits smooth transition from pwm to dc operation. in pwm operation the boot- strap capacitor is recharged each time top source pin goes low. as the duty cycle approaches 100% the output pulse width becomes narrower and the time available to produce an elevated upper mosfet gate supply becomes shorter than required. as the voltage across the bootstrap capacitor drops below 10.6v, an inductor-based switch- ing regulator kicks in and takes over the charging of the operatio u (refer to functional diagram) applicatio n s i n for m atio n wu u u mosfets. a diode connected between v + and the boost pin is still needed to allow conventional bootstrapping of the bootstrap capacitor when duty cycles are below 90%. the lt1336s internal switching regulator can provide enough charge to the bootstrap capacitor to allow the top driver to drive several power mosfets in parallel at its maximum operating frequency. the regulated voltage across v boost C v tsource is 10.6v; when this voltage is exceeded due to normal bootstrap action, the regulator automatically shuts down. the switching regulator uses a hysteretic current mode control. this method of control is simple, inherently stable and provides peak inductor current limit in every cycle. it is designed to run at a nominal frequency of around 700khz which is 7 the maximum pwm operating fre- quency of the lt1336. since the hysteretic current mode control has no internal oscillator, the frequency is deter- mined by external conditions such as supply voltage and load currents and external components such as inductor value and current sense resistor value. deriving the floating supply in a typical half-bridge driver like the lt1158 or the lt1160, the floating supply for the topside driver is provided by a bootstrap capacitor. this capacitor is re- charged each time its negative plate goes low in pwm operation. as the duty cycle approaches 100% the output pulse width becomes narrower and the time available to recharge the bootstrap capacitor becomes shorter than required (1 m s to 2 m s). for instance, at 100khz and at 95% duty cycle the output pulse width is only 0.5 m s; clearly this is insufficient time to recharge the capacitor by bootstrapping. to get around this problem, the lt1336 incorporates a switching regulator to help recharge the bootstrap capacitor under such extreme conditions. the lt1336 provides all the necessary circuitry to con- struct a boost or flyback switching regulator. this regula- tor can charge the bootstrap capacitor when it cannot recharge by bootstrapping. this happens when nearing 100% duty cycle in pwm applications. this is a worst- case condition because the bootstrap capacitor must still provide for the gate charging current of the high side
10 lt1336 applicatio n s i n for m atio n wu u u in applications where switching is always above 10khz and the duty cycle never exceeds 90%, pins 1, 15 and 16 can be left open. the bootstrap capacitor is then charged by conventional bootstrapping. only a diode needs to be connected between v + and the boost pin. a 0.1 m f boot- strap capacitor is usually adequate using this technique for driving a single mosfet under 10,000pf. when driv- ing multiple mosfets in parallel, if the total gate capaci- tance exceeds 10,000pf, the bootstrap capacitor should be increased proportionally above 0.1 m f (see paralleling mosfets). deriving the floating supply with the boost topology the advantage of using the boost topology is its simplicity. only a resistor, a small inductor, a diode and a capacitor are needed. however, the high voltage rail may not exceed 40v to avoid reaching the collector-base breakdown volt- age of the internal npn switch. the recommended values for the current sense resistor, inductor and bootstrap capacitor are 2 w , 200 m h and 1 m f respectively. using the recommended component values the boost regulator will run at around 700khz. to lower the frequency the inductor value can be increased and to increase the frequency the inductor value can be de- creased. the sense resistor should be at least 1.5 w to maintain adequate inductor current limit. the bootstrap capacitor value should be 1 m f or larger to minimize ripple voltage. an example of a boost regulator is shown in figure 1. figure 1. using the boost regulator switch sv + pv + r sense 2 w 1/4w c boost 1 m f d2 1n4148 s hv = 40v max + v boost 1336 f01 lt1336 200 m h* d1 1n4148 * sumida rcr-664d-221kc + + swgnd i sense tgatedr tgatefb boost tsource the boost regulator works as follows: when switch s is on, the inductor current ramps up as the magnetic field builds up. during this interval energy is being stored in the inductor and no power is transferred to v boost . when the inductor peak current is reached, sensed by the 2 w resistor, the switch is turned off. energy is no longer transferred to the inductor causing the magnetic field to collapse. the collapsing magnetic field induces a change in voltage across the inductor. the switch pin voltage rises until diode d2 starts conducting. as the inductor current ramps down, the lower inductor current threshold is reached and switch s is turned off, thus completing the cycle. current drawn from v + is delivered to v boost . some of this current (~ 1.5ma) flows through the topside driver to the top source pin. this current is typically returned to ground via the bottom mosfet or the output load. if the bottom mosfet were off and the output load were re- turned to hv, then the top source pin will return the current to hv through the top mosfet or the output load. if the hv supply cannot sink current and no load drawing greater than 1.5ma is connected to the supply, then a resistor from hv to ground may be needed to prevent voltage buildup on the hv supply. note that the current drawn from v + and delivered to v boost is significantly higher than the current drawn from v boost as given by: ii v v in v out boost + ? ? ? + = ? ? ? ? deriving the floating supply with the flyback topology for applications where the high voltage rail is greater than 40v, the flyback topology must be used. to configure a flyback regulator, a resistor, a diode, a small 1:1 turns ratio transformer and a capacitor are needed. the maximum voltage across the switch, assuming an ideal transformer, will be about v + + 11.3v. leakage inductance in nonideal transformers will induce an overvoltage spike at the switch at the instant when it opens. these spikes can be clamped using a snubbing network or a zener. unlike the boost topology, the current drawn from v + (assuming no loss) is equal to the current drawn from v boost .
11 lt1336 applicatio n s i n for m atio n wu u u using the components as shown in figure 2 the flyback regulator will run at around 800khz. to lower the fre- quency c filter can be increased and to increase the frequency c filter can be decreased. power mosfet selection since the lt1336 inherently protects the top and bottom mosfets from simultaneous conduction, there are no size or matching constraints. therefore, selection can be made based on the operating voltage and r ds(on) require- ments. the mosfet bv dss should be at least equal to the lt1336 absolute maximum operating voltage. for a maxi- mum operating hv supply of 60v, the mosfet bv dss should be from 60v to 100v. the mosfet r ds(on) is specified at t j = 25 c and is generally chosen based on the operating efficiency re- quired as long as the maximum mosfet junction tem- perature is not exceeded. the dissipation in each mosfet is given by: pdi r ds ds on = () + () ( ) 2 1 ? where d is the duty cycle and ? is the increase in r ds(on) at the anticipated mosfet junction temperature. from this equation the required r ds(on) can be derived: r p di ds on ds ( ) = () + () 2 1 ? for example, if the mosfet loss is to be limited to 2w when operating at 5a and a 90% duty cycle, the required r ds(on) would be 0.089 w /(1 + ? ). (1 + ? ) is given for each mosfet in the form of a normalized r ds(on) vs tempera- ture curve, but ? = 0.007/ c can be used as an approxima- tion for low voltage mosfets. thus, if t a = 85 c and the available heat sinking has a thermal resistance of 20 c/w, the mosfet junction temperature will be 125 c and ? = 0.007(125 C 25) = 0.7. this means that the required r ds(on) of the mosfet will be 0.089 w /1.7 = 0.0523 w , which can be satisfied by an irfz34 manufactured by international rectifier. transition losses result from the power dissipated in each mosfet during the time it is transitioning from off to on, or from on to off. these losses are proportional to (f)(hv) 2 and vary from insignificant to being a limiting factor on operating frequency in some high voltage applications. figure 2. using the flyback regulator the flyback regulator works as follows: when switch s is on, the primary current ramps up as the magnetic field builds up. the magnetic field in the core induces a voltage on the secondary winding equal to v + . however, no power is transferred to v boost because the rectifier diode d2 is reverse biased. the energy is stored in the transformers magnetic field. when the primary inductor peak current is reached, the switch is turned off. energy is no longer transferred to the transformer causing the magnetic field to collapse. the collapsing magnetic field induces a change in voltage across the transformers windings. during this transition the switch pins voltage flies to 10.6v plus a diode above v + , the secondary forward biases the rectifier diode d2 and the transformers energy is transferred to v boost . meanwhile the primary inductor current goes to zero and the voltage at i sense decays to the lower inductor current threshold with a time constant of (r sense )(c filter ), thus completing the cycle. switch sv + pv + r sense 2 w 1/4w d2 1n4148 40v 1n4148 24v 1000pf 6.2k s hv = 60v max 1336 f02 lt1336 t1* 1:1 d1 1n4148 * coiltronics ctx100-1p + swgnd i sense c boost 1 m f c filter 0.1 m f + v boost + tgatedr tgatefb boost tsource
12 lt1336 applicatio n s i n for m atio n wu u u paralleling mosfets when the above calculations result in a lower r ds(on) than is economically feasible with a single mosfet, two or more mosfets can be paralleled. the mosfets will inherently share the currents according to their r ds(on) ratio as long as they are thermally connected (e.g., on a common heat sink). the lt1336 top and bottom drivers can each drive five power mosfets in parallel with only a small loss in switching speeds (see typical performance characteristics). a low value resistor (10 w to 47 w ) in series with each individual mosfet gate may be required to decouple each mosfet from its neighbors to prevent high frequency oscillations (consult manufacturers rec- ommendations). if gate decoupling resistors are used, the corresponding gate feedback pin can be connected to any one of the gates as shown in figure 3. driving multiple mosfets in parallel may restrict the operating frequency to prevent overdissipation in the lt1336 (see the following gate charge and driver dissipation). the actual increase in supply current is slightly higher due to lt1336 switching losses and the fact that the gates are being charged to more than 10v. supply current vs switching frequency is given in the typical performance characteristics. the lt1336 junction temperature can be estimated by using the equations given in note 1 of the electrical characteristics. for example, the LT1336IS is limited to less than 31ma from a 12v supply: t j = 85 c + (31ma)(12v)(110 c/w) = 126 c exceeds absolute maximum in order to prevent the maximum junction temperature from being exceeded, the lt1336 supply current must be verified while driving the full complement of the chosen mosfet type at the maximum switching frequency. ugly transient issues in pwm applications the drain current of the top mosfet is a square wave at the input frequency and duty cycle. to prevent large voltage transients at the top drain, a low esr electrolytic capacitor must be used and returned to the power ground. the capacitor is generally in the range of 25 m f to 5000 m f and must be physically sized for the rms current flowing in the drain to prevent heating and prema- ture failure. in addition, the lt1336 requires a separate 10 m f capacitor connected closely between pins 2 and 6. the lt1336 top source is internally protected against transients below ground and above supply. however, the gate drive pins cannot be forced below ground. in most applications, negative transients coupled from the source to the gate of the top mosfet do not cause any problems. switching regulator applications the lt1336 is ideal as a synchronous switch driver to improve the efficiency of step-down (buck) switching regulators. most step-down regulators use a high current schottky diode to conduct the inductor current when the switch is off. the fractions of the oscillator period that the switch is on (switch conducting) and off (diode conduct- ing) are given by: figure 3. paralleling mosfets gatedr gatefb lt1336 r g * r g * hv *optional 10 w 1336 f03 + gate charge and driver dissipation a useful indicator of the load presented to the driver by a power mosfet is the total gate charge q g , which includes the additional charge required by the gate-to-drain swing. q g is usually specified for v gs = 10v and v ds = 0.8v ds(max) . when the supply current is measured in a switching application, it will be larger than given by the dc electrical characteristics because of the additional supply current associated with sourcing the mosfet gate charge: ii dq dt dq dt supply dc g top g bottom =+ ? ? ? ? + ? ? ? ?
13 lt1336 applicatio n s i n for m atio n wu u u figure 4. adding synchronous switching to a step-down switching regulator negative inductor current is returned to hv when the switch turns back on. however, i 2 r losses will occur under these conditions due to the recirculating currents. the lt1336 performs the synchronous mosfet drive in a step-down switching regulator. a reference and pwm are required to complete the regulator. any voltage mode or current mode pwm controller may be used but the lt3526 is particularly well-suited to high power, high efficiency applications such as the 10a circuit shown in figure 6. in higher current regulators a small schottky diode across the bottom mosfet helps to reduce reverse- recovery switching losses. motor drive applications in applications where rotation is always in the same direction, a single lt1336 controlling a half-bridge can be used to drive a dc motor. one end of the motor may be connected either to supply or to ground. a motor in this configuration is controlled by its inputs which give three alternatives: run, free running stop (coasting) and fast stop (plugging braking with the motor shorted by one of the mosfets). whenever possible, returning one end of the motor to ground is preferable. when the motor is returned to supply and the boost topology is used to charge the bootstrap capacitor, the return current from the top driver will find its way to the high voltage rail through the top mosfet. since + + intop inbottom tgatedr tgatefb tsource bgatedr bgatefb lt1336 hv v out r gs r sense 1336 f04 ref pwm out a out a switch total period switch total period on = v hv off = hv v hv out out ? ? ? ? () ? ? ? ? () note that for hv > 2v out , the switch is off longer than it is on, making the diode losses more significant than the switch. the worst case for the diode is during a short circuit, when v out approaches zero and the diode con- ducts the short-circuit current almost continuously. figure 4 shows the lt1336 used to synchronously drive a pair of power mosfets in a step-down regulator applica- tion, where the top mosfet is the switch and the bottom mosfet replaces the schottky diode. since both conduc- tion paths have low losses, this approach can result in very high efficiency (90% to 95%) in most applications. for regulators under 10a, using low r ds(on) n-channel mosfets eliminates the need for heat sinks. r gs holds the top mosfet off when hv is applied before the 12v supply. one fundamental difference in the operation of a step- down regulator with synchronous switching is that it never becomes discontinuous at light loads. the inductor cur- rent doesnt stop ramping down when it reaches zero, but actually reverses polarity, resulting in a constant ripple current independent of load. this does not cause a signifi- cant efficiency loss (as might be expected) since the
14 lt1336 most power supplies cannot sink current, this current can raise the voltage of the high voltage rail. this can be avoided by placing a discharge resistor between hv sup- ply and ground to divert the return current to ground as shown in figure 5. for a high voltage rail of 40v, a 26k resistor or smaller should be used, since the top driver will return about 1.5ma. for applications where using a discharge resistor is unde- sirable, use the flyback regulator topology instead of the boost regulator topology (see deriving the floating supply with the flyback topology). to drive a dc motor in both directions, two lt1336s can be used to drive an h-bridge output stage. in this configu- ration the motor can be made to run clockwise, counter- clockwise, stop rapidly (plugging braking) or free run (coast) to a stop. a very rapid stop may be achieved by reversing the current, though this requires more careful design to stop the motor dead. in practice a closed-loop control system with tachometric feedback is usually necessary. applicatio n s i n for m atio n wu u u the motor speed in these examples can be controlled by switching the drivers with pulse width modulated square waves. this approach is particularly suitable for micro- computers/dsp control loops. figure 6. 90% efficiency, 40v to 5v, 10a, low dropout voltage mode switching regulator v + v + switch boost tgatedr tgatefb tsource bgatedr bgatefb pgnd lt1336 i sense d1 1n4148 d2 1n4148 c boost 1 m f 1336 f05 hv = 40v max + + r sense 2 w 1/4w r dischrg 24k *sumida rcr-664d-221kc 200 m h* 10 m f + + v boost figure 5. driving a supply referenced motor typical applicatio n s u + + + + + + 2.2nf 27k 0.1 m f 1k 1k 5k 2k 5v 5400 m f low esr 1336 f06 1 m f 10 m f 1 m f 1 m f 0.022 m f c1 0.1 m f 360 w 510 w 4.7k 0.33 m f 330k 12v 1n4148 1n4148 irfz44 irfz44 mbr340 * sumida rcr-664d-221kc ** magnetics core #55585-a2 30 turns 14ga magnet wire ? dale type lvr-3 ultronix rcs01 irfz44 40v 2200 m f ea low esr r s ? 0.007 w l2** 70 m h f = 25khz 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 l1* 200 h r sense 2 w, 1/4w switch swgnd boost tgatedr tgatefb tsource pv + bgatedr lt1336 i sense sv + intop inbottom uvout sgnd pgnd bgatefb shutdown + 2n2222 1n4148 0.1 m f 4.7k 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 lt3526 1n4148
15 lt1336 typical applicatio n s u kool m m is a registered trademark of magnetics, inc. + 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 8 7 6 5 16 15 14 13 12 11 10 9 1 2 3 4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 + 1 2 3 4 5 6 7 14 13 12 11 10 9 8 lt1058 tc4428 l* 158 m h 330k irfz44 irfz44 irfz44 irfz44 10 m f 150k 10k 100k 95k 1336 f07 150k 12v 10k 10k 200k 95k 10k 10k 200k in 5v 1k 1k 1k 1k 12v 0.0033 m f 0.1 m f 0.1 m f 1 m f 0.0033 m f 1k 47 m f 47 m f 47 m f 0.1 m f 100 m f 0.1 m f 10 m f 10 m f 0.1 m f 1000 m f + 1000 m f 1n4148 0.1 m f 1n4148 330k load + + lt1015 lt1016 + + 10k 10k 10k + + * kool m m ? core #77548-a7 35 turns 14ga magnet wire f carrier = 100khz 60v max switch swgnd boost tgatedr tgatefb tsource pv + bgatedr lt1336 i sense sv + intop inbottom uvout sgnd pgnd bgatefb switch swgnd boost tgatedr tgatefb tsource pv + bgatedr lt1336 i sense sv + intop inbottom uvout sgnd pgnd bgatefb l* 158 m h 10 m f + + 47 m f + figure 7. 200w class d, 10hz to 1khz amplifier information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 lt1336 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0796 7k ? printed in usa ? linear technology corporation 1996 typical applicatio n s u part number description comments lt1158 half-bridge n-channel power mosfet driver single input, continuous current protection and internal charge pump for dc operation lt1160 half-bridge n-channel power mosfet driver one input per channel, 60v high voltage supply rail and undervoltage protection lt1162 full-bridge n-channel power mosfet driver one input per channel, 60v high voltage supply rail and undervoltage protection related parts s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) n16 0695 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.015 (0.381) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) n package 16-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) package descriptio n u dimensions in inches (millimeters) unless otherwise noted. figure 8. 90% efficiency, 40v to 5v, 10a, low dropout current mode switching regulator s16 0695 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** + + + + 6800pf 100pf 10k 18k 18k 10k 2k 1k 1k 5k 25k 500k 5v 5400 m f low esr 1136 f08 0.1 m f 10 m f 2.2 m f + 1 m f 0.1 m f 330k 12v 1n4148 1n4148 1n4148 4700pf irfz34 irfz44 mbr340 * hurricane lab hl-km147u ** dale type lvr-3 ultronix rcs01 irfz44 40v 2200 m f ea low esr r s ** 0.007 w l* 47 m h f = 40khz 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + q1 lt1846 switch swgnd boost tgatedr tgatefb tsource pv + bgatedr lt1336 i sense sv + intop inbottom uvout sgnd pgnd bgatefb

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